Cao, JiangLogoteta, DemetrioÖzkaya, ÖzkayaBiel, BlancaCresti, AlessandroPala, MarcoEsseni, David13.07.20192019-07-1613.07.20192019-07-16201597814673989300163-1918https://dx.doi.org/10.1109/IEDM.2015.7409684https://hdl.handle.net/20.500.12451/2473IEEE Electron Devices Society61st IEEE International Electron Devices Meeting, IEDM 2015 -- 7 December 2015 through 9 December 2015 -- -- 119534We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay. © 2015 IEEE.eninfo:eu-repo/semantics/openAccessConference Object2016-February12.05.200112.05.200410.1109/IEDM.2015.7409684Q2N/A